TRCD-26-05276
Senior Post-Silicon Validation / Emulation Engineer (Cadence Palladium)
Senior-level engineer (5–8 years) needed for post-silicon debug and issue reproduction on Cadence Palladium emulation. The role focuses on bringing up and running/porting software tests on Palladium, reproducing silicon issues in emulation, debugging common peripheral protocols (UART/SPI/I2C), and developing validation tests in C and in a post-silicon bench that is largely Python-controlled.
Position summary
- Location
- India
- Workplace
- On-site
- Employment
- Contract
- Experience
- Minimum 5 years and Maximum 8 years
Role overview
Why This Role Matters.
Senior-level engineer (5–8 years) needed for post-silicon debug and issue reproduction on Cadence Palladium emulation. The role focuses on bringing up and running/porting software tests on Palladium, reproducing silicon issues in emulation, debugging common peripheral protocols (UART/SPI/I2C), and developing validation tests in C and in a post-silicon bench that is largely Python-controlled.
Your Impact
Deliver Enterprise Value
Help organisations solve complex business problems through modern technology, consulting expertise and measurable outcomes.
Collaboration
Work Across Teams
Collaborate with consultants, architects, engineers and client stakeholders throughout the project lifecycle.
Growth
Learn Continuously
Gain exposure to enterprise technologies, certifications, mentoring and real-world project experience.
Career Path
Grow With Ubique
Build a long-term consulting career with opportunities to take on greater responsibility and leadership over time.
Responsibilities
What You'll Be Doing.
Every role at Ubique contributes directly to solving meaningful business challenges for our clients.
§ Reproduction of Si issues on palladium
§ Running/ porting SW tests on palladium
§ Peripheral (uart, spi, i2c etc) protocol and debug knowledge
§ Writing tests cases in post Si bench (mostly Py controlled)
Technology stack
Tools & Technologies.
The platforms and technologies you'll use to build modern, enterprise-grade solutions.
Cadence Palladium
emulation
Palladium flows
post-silicon debug
post-silicon validation
silicon issue reproduction
SW tests
C
Python
UART
SPI
I2C
protocol debug
post-Si bench
Requirements
Skills & Experience.
We value curiosity, collaboration and continuous learning. If you don't meet every requirement but believe you can make an impact, we'd still love to hear from you.
Essential
Required Qualifications
Cadence Palladium emulation flows (setup, compile, run, debug)
Post-silicon debug experience
Reproducing silicon (Si) issues on Palladium emulation
Running and porting software tests on Palladium
Peripheral protocol knowledge and debug: UART, SPI, I2C
Writing C test cases
Writing test cases in a post-silicon bench (Python-controlled)
Preferred
Nice to Have
General hardware/software co-debug skills (firmware + emulation)
Test automation/scripting in Python beyond basic usage
Experience with additional peripheral protocols beyond UART/SPI/I2C
What you'll gain
More Than Just A Job.
We're committed to helping every team member grow professionally, personally and technically while working on meaningful projects.
Global Exposure
Collaborate with international clients and multicultural teams on enterprise programmes.
Continuous Learning
Expand your expertise through mentoring, certifications and hands-on project experience.
Career Growth
Take ownership, develop leadership skills and grow your consulting career over time.
Flexible Working
Hybrid and remote collaboration designed around trust and delivering exceptional outcomes.
People First
Join a supportive culture where collaboration, respect and long-term relationships come first.
Enterprise Projects
Work on meaningful technology initiatives for leading organisations across industries.
Apply
Apply for Senior Post-Silicon Validation / Emulation Engineer (Cadence Palladium)
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